NAND in CMOS Logic

Below is a circuit diagram of NAND in CMOS logic.
NAND in CMOS logic

The circuit is made of two pairs with nMOS and cMOS, each of which has a common input, A and B, respectively.
Actually two points of a common input should be drawn to branched from the same source, nonetheless such branches are omitted to simplify the diagram.

This arrangement is explained by the truth table.
Truth table of NAND

The above table is not written in HTML, but a located pict file, because I didn’t like to take a trouble in showing a “bar” above “A·B”.

The table shows only when all inputs to nMOS and pMOS are positive the output will be zero.
This is realized as the picture below shows.
NAND, A=0, B=0
(The figure above has been replaced on 9/28)

As the figure above indicates, no charge is supplied to pMOS and all charges are lost to the ground through nMOS, the output comes to 0.
As a matter of fact, when all inputs to nMOS are positive, the output will be zero, whatever inputs to pMOS would be, because all charges will lost to the ground.

In other case, for example, when only the input to B is zero, the out put will be positive, because the current passes one pMOS of the two arrayed parallel, and is kept from being lost lost at one nMOS of the two arrayed serial.
NAND, A=0, B=1

Another example is when all inputs to nMOS and pMOS are zero the output will be positive. In this case all pMOS are open and the current flows, but the output isn’t affected by the number of open pMOS, because they are arranged parallel.
NAND, A=0, B=0

Based on some of these examples, the below is what is to be remembered about NAND in CMOS logic.

nMOS: serial, pMOS: parallel

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